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Items where Author is "Sallese, Jean-Michel"

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Number of items: 3.

Article

Grabinski, Wladek, Pavanello, Marcelo, De Souza, Michelly, Tomaszewski, Daniel, Malesinska, Jola, Głuszko, Grzegorz, Bucher, Matthias, Makris, Nikolaos, Nikolaou, Aristeidis, Abo-Elhadid, Ahmed, Mierzwinski, Marek, Lemaitre, Laurent, Brinson, Mike, Lallement, Christophe, Sallese, Jean-Michel, Yoshitomi, Sadayuki, Malisse, Paul, Oguey, Henri, Cserveny, Stefan, Enz, Christian, Krummenacher, François and Vittoz, Eric (2019) FOSS EKV2.6 at GitHub. Arbeitskreis Modellierung von Systemen und Parameterextraktion ( Modeling of Systems and Parameter Extraction Working Group).

Brinson, Mike, Grabinski, Wladek, Pavanello, Marcelo, De Souza, Michelly, Tomaszewski, Daniel, Malesinska, Jola, Głuszko, Grzegorz, Bucher, Matthias, Makris, Nikolaos, Nikolaou, Aristeidis, Abo-Elhadid, Ahmed, Mierzwinski, Marek, Lemaitre, Laurent, Lallement, Christophe, Sallese, Jean-Michel, Yoshitomi, Sadayuki, Malisse, Paul, Oguey, Henri, Cserveny, Stefan, Enz, Christian, Krummenacher, François and Vittoz, Eric (2019) FOSS EKV2.6 Verilog-A Compact MOSFET Model. Proceedings of ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC). pp. 190-193. ISSN ISBN: 978-1-7281-1539-9

Conference or Workshop Item

Grabinski, Wladek, Scholz, Rene, Verley, Jason, Keiter, Eric R., Vogt, Holger, Warning, Dietmar, Nenzi, Paolo, Lannutti, Francesco, Salfelder, Felix, Davis, Al, Brinson, Mike, Virdee, Bal Singh, Torri, Guilherme B., Tomaszewski, Daniel, Bucher, Matthias, Sallese, Jean-Michel, Muller, Markus, Kuthe, Pascal and Krattenmacher, Mario (2024) FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs. In: 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 03-06 March 2024, Bangalore, India.

This list was generated on Wed Nov 20 21:22:52 2024 UTC.