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Grabinski, Wladek, Scholz, Rene, Verley, Jason, Keiter, Eric R., Vogt, Holger, Warning, Dietmar, Nenzi, Paolo, Lannutti, Francesco, Salfelder, Felix, Davis, Al, Brinson, Mike, Virdee, Bal, Torri, Guilherme B., Tomaszewski, Daniel, Bucher, Matthias, Sallese, Jean-Michel, Muller, Markus, Kuthe, Pascal and Krattenmacher, Mario (2024) FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs. In: 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 03-06 March 2024, Bangalore, India.
Grabinski, Wladek, Brinson, Mike, Nenzi, Paolo, Lannutti, Francesco, Makris, Nikolaos, Antonopoulos, Anglos and Bucher, Matthias (2014) Open source circuit simulation tools for RF compact semiconductor device modelling. International Journal of Numerical Modelling: Electronic Networks, Devices, Networks and Fields: Special Issue: Modelling of High‐Frequency Silicon Transistors (Invited paper), 27 (5-6). pp. 761-779. ISSN 0894-3370
Brinson, Mike, Jahn, Stefan, Margraf, Michael, Parruitte, Hélène, Ardouin, B., Nenzi, Paolo and Lemaitre, Laurent (2007) GNU simulators supporting Verilog-A compact model standardization. In: MOS-AK international Meeting, 20 April 2007, Premstaetten, Germany.