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GNU simulators supporting Verilog-A compact model standardization

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Brinson, Mike, Jahn, Stefan, Margraf, Michael, Parruitte, Hélène, Ardouin, B., Nenzi, Paolo and Lemaitre, Laurent (2007) GNU simulators supporting Verilog-A compact model standardization. In: MOS-AK international Meeting, 20 April 2007, Premstaetten, Germany.

Abstract

This poster explains about Qucs: Quite Universal Circuit Simulator, ADMS: Verilog-A Compact Model Generator and NGSpice: mixed-level/mixed-signal circuit simulator.

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Title:
GNU simulators supporting Verilog-A compact model standardization
Creators:
Brinson, Mike, Jahn, Stefan, Margraf, Michael, Parruitte, Hélène, Ardouin, B., Nenzi, Paolo and Lemaitre, Laurent
Date:
20 April 2007
Subjects:
600 Technology > 620 Engineering & allied operations
Department:
School of Computing and Digital Media
Uncontrolled Keywords:
Quite Universal Circuit Simulator (Qucs); Verilog-A compact model generator (ADMS); Next Generation SPICE (Ngspice)
Record
URI:
https://repository.londonmet.ac.uk/id/eprint/5260
Item Type:
Conference or Workshop Item
Presentation Type:
Poster
Depositing User:
Mike Brinson
Date Deposited:
04 Nov 2019 10:00
Revision:
10
Last Modified:
04 Nov 2019 10:00
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