Z domain delay subcircuits and compact Verilog-A macromodels for mixed-mode sampled data circuit simulation

Brinson, Mike and Nabijou, Hassan (2009) Z domain delay subcircuits and compact Verilog-A macromodels for mixed-mode sampled data circuit simulation. Radioelectronics and Informatics Journal, 2. pp. 14-20. ISSN 1563-0064

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Abstract / Description

Mixed-mode simulation is an important circuit design and system testing tool for established and emerging semiconductor sampled data technologies. This paper describes a number of functional, computationally efficient, Z domain delay models, outlining the role of current and charge equations in the construction of subcircuit and compact Verilog-A delay macromodels. To illustrate the properties of the proposed macromodels a number of Qucs (Quite universal circuit simulator) transient and frequency domain simulation examples are presented. Each of these stresses the use of test and data extraction techniques which are not easily undertaken with the SPICE 2g6 or 3f5 simulators.

Item Type:	Article
Uncontrolled Keywords:	Mixed-mode sampled data circuit simulation;Functional delay subcircuits; Compact Verilog-A delay macro-models; Qucs (Quite universal circuit simulator)
Subjects:	600 Technology > 620 Engineering & allied operations
Department:	School of Computing and Digital Media
Depositing User:	Mike Brinson
Date Deposited:	31 Oct 2019 09:22
Last Modified:	31 Oct 2019 09:22
URI:	https://repository.londonmet.ac.uk/id/eprint/5255

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