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Brinson, Mike (2019) Equation-defined template and synthesis driven compact modelling of semiconductor devices. In: IEEE EDS DL Mini-Colloquium, 26 June 2019, IEEE Region 8 (Europe, Middle East and Africa), ED Poland Chapter "Nanoelectronics - Technology, Design, Modeling".
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EDSDLMQL2019.pdf - Published Version Available under License Creative Commons Attribution No Derivatives 4.0. Download (2MB) | Preview |
Abstract / Description
The rapid expansion in emerging semiconductor devices has led to the need for improved compact modelling and circuit simulation tools. In order to achieve wide spread acceptance of any new modelling tool it must be simple to use, generate device models that produce accurate simulation data, simulate at practical speeds, meet international hardware description language standards and be freely available to the compact modelling community. This presentation reports on current research that links Equation-Defined Device modelling with Verilog-A modules, driven by code templates and synthesis, which in turn result in an improved interactive modelling technique that can be employed to construct compact models that have a similar performance to compiled C++ code models. Throughout the talk a series of compact device models will be introduced to demonstrate the fundamentals and application of the new approach to compact device modelling.
| Item Type: | Conference or Workshop Item (Lecture) |
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| Uncontrolled Keywords: | semiconductor device modelling, Equation-Defined Devices (EDD), Verilog-A modules, C++ code models |
| Subjects: | 600 Technology > 620 Engineering & allied operations |
| Department: | School of Computing and Digital Media |
| Depositing User: | Mike Brinson |
| Date Deposited: | 17 Sep 2019 11:38 |
| Last Modified: | 17 Sep 2019 11:38 |
| URI: | https://repository.londonmet.ac.uk/id/eprint/5110 |
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