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Grabinski, Wladek, Scholz, Rene, Verley, Jason, Keiter, Eric R., Vogt, Holger, Warning, Dietmar, Nenzi, Paolo, Lannutti, Francesco, Salfelder, Felix, Davis, Al, Brinson, Mike, Virdee, Bal Singh, Torri, Guilherme B., Tomaszewski, Daniel, Bucher, Matthias, Sallese, Jean-Michel, Muller, Markus, Kuthe, Pascal and Krattenmacher, Mario (2024) FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs. In: 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 03-06 March 2024, Bangalore, India.
The semiconductor industry continues to grow and innovate; however, companies are facing challenges in growing their workforce with skilled technicians and engineers. To meet the demand for well-trained workers worldwide, innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem are of utmost importance. FOSS CAD/EDA tools combined with free and open-access PDKs can serve as a new platform for bringing together IC design newbies, enthusiasts, and experienced mentors.
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