FOSS EKV2.6 Verilog-A Compact MOSFET Model

Brinson, Mike, Grabinski, Wladek, Pavanello, Marcelo, De Souza, Michelly, Tomaszewski, Daniel, Malesinska, Jola, Głuszko, Grzegorz, Bucher, Matthias, Makris, Nikolaos, Nikolaou, Aristeidis, Abo-Elhadid, Ahmed, Mierzwinski, Marek, Lemaitre, Laurent, Lallement, Christophe, Sallese, Jean-Michel, Yoshitomi, Sadayuki, Malisse, Paul, Oguey, Henri, Cserveny, Stefan, Enz, Christian, Krummenacher, Franço and Vittoz, Eric (2019) FOSS EKV2.6 Verilog-A Compact MOSFET Model. In: ESSDERC 49th European Solid-State Devices Conference, 23-26 September 2019, Krakow, Poland. (In Press)

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Abstract / Description

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: EKV2.6 model; compact/SPICE model; Verilog-A
Subjects: 600 Technology
600 Technology > 620 Engineering & allied operations
Department: School of Computing and Digital Media
Depositing User: Mike Brinson
Date Deposited: 17 Sep 2019 12:09
Last Modified: 17 Sep 2019 12:09
URI: http://repository.londonmet.ac.uk/id/eprint/5112

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