Current Conveyor Equation-Defined Macromodels for Wideband RF Circuit Design

Brinson, Mike and Kuznetsov, Vadim (2017) Current Conveyor Equation-Defined Macromodels for Wideband RF Circuit Design. International Journal of Microelectronics and Computer Science. pp. 65-71. ISSN 2080-8755 (Submitted)

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Abstract

A high percentage of analogue integrated circuit designs use voltage domain signal processing techniques. Given the fact that integrated circuit current conveyors are high bandwidth current processing devices, often with superior RF performance compared to comparable voltage domain devices, it is surprising that the number of current mode integrated circuits available, as standard of-the-shelf industrial items, is so small. This paper introduces equation-defined device and Verilog-A synthesis approaches to the macromodelling of current conveyor integrated circuits. To illustrate the proposed modelling techniques the properties of a number of modular behavioural level current conveyor macromodel cells are described and their performance compared. The material presented is intended for analogue device modellers and circuit designers who wish to simulate large signal current domain integrated circuit designs.It also demonstrates how synthesized Verilog-A modules can be derived from equation-defined device and conventional subcircuits to form functional, computationally efficient current conveyor macromodels. To illustrate the application of behavioural current conveyor macromodels the design of a six cell CCII+ instrumentation amplifier is introduced and its performance discussed.

Item Type: Article
Uncontrolled Keywords: Qucs, current conveyors, compact semiconductor device modelling, equation-defined devices, macromodels, Verilog-A module synthesis
Subjects: 600 Technology > 620 Engineering & allied operations
Department: School of Computing and Digital Media
Depositing User: Bal Virdee
Date Deposited: 08 Jan 2018 11:07
Last Modified: 08 Jan 2018 11:07
URI: http://repository.londonmet.ac.uk/id/eprint/1324

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